modulus;
| parametri nomen | attributum valorem |
| Estne Rohs certificatus? | occurrat |
| Commercium Nomina | XILINX (Xilinx) |
| Obsequium Code | compli |
| ECCN code | 3A991.D |
| maxime horologium frequency | 667 MHz |
| JESD-30 code | S-PBGA-B484 |
| JESD-609 codice | e1 |
| Umor sensus Level | 3 |
| numerus entries | 338 |
| Numerus unitas rationis | 147443 |
| output temporibus | 338 |
| Numerus terminalum | 484 |
| Sarcina corpus materiale | Plastic/EPOXY |
| sarcina codice | FBGA |
| Equivalent code encapsulate | BGA484,22X22,32 |
| Package figura | QUADRATUM |
| Forma sarcina | GRID ACIES, PIX |
| Pecco Reflow Temperature (Celsius) | 260 |
| potentia copia | 1.2,1.2/3.3,2.5/3.3 V |
| Programmabilis Logica Type | AGRUM PROGRAMMABILIS PORTA ACIES |
| Certification status | Non secundum quid |
| superficies montis | ETIAM' |
| technologia | CMOS |
| Terminatio superficies | stannum argenteum |
| Terminatio forma | SPHERA |
| Terminatio picis | 0.8 mm |
| Terminatio locus | BOTTOM |
| Maximum tempus ad apicem reflow temperatus | 30 |
Communia :
Xilinx® 7 series FPGAs comprehendunt quattuor familias FPGA, quae integram amplitudinem systematis requiruntur, e parvo pretio, parva forma factoris vagantes;
cost-sensitivum, altum volumen applicationes ad finem connectivity ultra longitudinis, capacitatis logicae, et insignem processui facultatem pro gravissima
summus effectus est.Series VII FPGAs includit:
• Spartan®-7 Family: Optimized for low cost, infima potestas, and high
I/O perficiendi.Available in parvo pretio, valde parva forma factoris
packaging pro minimo PCB vestigium.
• Artix®-7 Genus: Optimised ad vim applicationes humilis Vide requirens
transceptores et alta DSP et logica throughput.Ima praebet
summa rogationis materiae sumptus pro summus throughput, cost-sensitivo
utilibus.
• Kintex®-VII Genus: Optimized pro optimo pretio-perficiendi cum 2X
melius comparatur generationi priori, ut novum genus
of FPGAs.
• Virtex®-7 Genus: Optimized pro summa ratio perficiendi et
facultatem cum 2X emendationem in systemate perficiendi.altissimum
facultatem machinas per reclinant Pii interconnect (SSI)
amplificatur.
Super statu-de arte, summus perficientur, humilis potentia (HPL), 28 um, summus k porta metallica (HKMG) processus technologiae, 7 series FPGAs efficiunt
2.9 Tb/s of I/O band, 2.9 million logic cell facultatem, 5.3 TMAC/s DSP incomparabili incremento cum 2.9 Tb/s of I/O
potentia quam cogitationes generationis antecedens ut ASSPs et ASICs plene programmabilem offerant.
Summary of 7 Series FPGA Features
• Provectus summus perficientur FPGA logica secundum realem 6-input aspectum
mensa (LUT) technologiae configurable ut memoriae distributa.
• 36 Kb dual-portus scandalum RAM cum aedificatis in FIFO logicis pro in-chip data
buffering.
• High-perficiendi SelectIO™ technology cum auxilio DDR3
interfaces usque ad 1,866 Mb/s.
• Vide connectivity summus celeritas cum transceivers multi gigabit constructum-
ab 600 Mb/s ad max.rates de 6.6 Gb/s usque ad 28.05 Gb/s, oblatio a
peculiaris humilis potentiae modus, optimized pro chip-ad-chip interfaces.
• A user configurable analog interface (XADC), incorporatio dualis
XII frenum 1MSPS analog-ad-digital converters cum on-chip scelerisque ac
supplere sensoriis.
• DSP pecias cum 25 x 18 multiplicatoris, accumulatoris 48-bit, et praecellentis aspis
pro summus perficientur eliquare, inter optimized symmetrica
coefficiens eliquare.
• Validus horologii procuratio tegularum (CMT) iungendo tempus-clausum
ansa (PLL) et horologium mixtum-modus procurator (MMCM) caudices ad altum
subtilitas et humilis Jitter.
• Celeriter processus embedded cum MicroBlaze™ processus explicas.
• Integrated scandalum PCI Express® (PCIe), usque ad x8 Gen3
Endpoint and Radix Portus designs.
• Lata varietas optionum configurationis, inter subsidium
mercimoniarum memoriam, 256-bit AES encryption cum HMAC/SHA-256
authenticas, constructas seu detectas et correctiones.
• Minimum-cost, filum-vinculum, nudum-moriturum flip-chip, et altae notae integritatis flip
chip packaging offering facilis migratio inter familia membra in
eadem sarcina.All packages available in PB-free and selected
packages in Pb option.
• Designed for high performance and lowest power with 28 um,
HKMG, HPL processus, 1.0V core processus technologiae voltage and
0.9V core intentione bene pro viribus etiam inferioribus.
