proprietatibus productum
| EXEMPLUM | PERSEQUOR |
| genus | Integrated Circuit (IC) Embedded - Microcontrollers |
| manufacturer | NXP USA Inc. |
| series | MPC56xx Qorivva |
| sarcina | lance |
| productum status | in stirpe |
| core processus | e200z0h |
| Kernel specificatio | XXXII frenum unum core |
| celeritas | 64MHz |
| Connectivity | CANbus，I²C，LIN，SCI，SPI |
| Peripherales | DMA POR PWM WDT |
| Numerus I / O | 79 |
| Facultatem repono Program | 512KB（512K x 8） |
| Program memoriae genus | micare |
| EEPROM facultatem | 64K x 8 |
| RAM magnitudine | 32K x 8 |
| Voltage - Power (Vcc/Vdd) | 3V ~ 5.5V |
| notitia converter | A/D 28x10b |
| Oscillator Type | internum |
| Operating Temperature | -40°C ~ 85°C (TA) |
| genus institutionem | Superficiem Monte Type |
| Sarcina / clausura | 100-LQFP |
| Supplementum Fabrica Packaging | 100-LQFP（14x14） |
| Basic productum numerus | SPC5604 |
Environment et Exportatio Classification:
| ATTRIBUTES | PERSEQUOR |
| RoHS status | Obsequium ROHS3 specificationem |
| Humorem Sensitivum Level (MSL) | III (CLXVIII horas) |
| SPATIUM status | Non products SPATIUM |
| EVASIT | 3A991A2 |
| HTSUS | 8542.31.0001 |
Features:
• Unius exitus, 32-bit CPU complexus (e200z0)
- Virtutis obsequium Architecture® embedded
genus
- Includes disciplinam set amplificationem permittens
differentiam longitudinis modum translitterandi (VLE) in codice vestigium magnitudinis
reductio.Cum ad libitum modum translitterandi mixti 16-bit
and 32-bit instructions, is possible to achieve
significativum codicem magnitudo vestigium reductionis.
• Sursum ad DXII KB, chip code mico fulta mico
moderatoris et ECC*
• 64 (4 16) KB on-chip notitia memoriae cum ECC
• Ad XLVIII KB in-chip SRAM cum ECC
• Memoria praesidium unitatis (MPU) cum VIII regione descriptores
ac XXXII-byte regione granularity
• Interrumpere moderatoris (INTC) cum 148 vectoribus interpellare;
interregem 16 extra fontes et 18 externum
adjicias / excitare fontes
• Frequency modulatur tempus-clausa loop (FMPLL)
• Crossbar switch architectura ad accessum ad concurrentem
peripherales, mico memoria, vel ram ex multiplici bus
domini
• Tabernus adiuvaret moduli (BAM) sustinet internum mico
programming per vinculum Vide (can vel SCI)
• Vicis subsidiis initus / output channels providens a range of
16-bit captio, output comparatio et latitudo leguminis
modulationis functiones (eMIOS-lite)
• 10-bit analog-ad-digital converter (ADC)
• 3 Vide interface periphericum (DSPI) modulorum
Vide communicationis interface ad • IV (LINFlex)
Modules
• Usque ad 6 aucta plena CAN (FlexCAN) moduli cum
configurable buffers
• 1 inter IC communicationis instrumenti (I2C) moduli
• Ad 123 configurable generalis consilii paxillos supportantes
initus et output res (dependens sarcina)
• Real Time Counter (RTC) cum fonte horologii from128 kHz
seu 16 MHz internus RC oscillator sui iuris sustinens
expergiscimini cum 1 MS senatus cum max timeout de 2
seconds
• Ad VI periodica interrumpere timers (PIT) cum XXXII frenum counter
resolutio
• 1 Systema Module Timer (STM)
• Nexus evolutionis interface (NDI) per IEEE-ISTO
5001-2003 Classis duae plus vexillum
• Fabrica / tabula terminus Scan probatio fulta per
Communem Test Actionis Group (JTAG) IEEE (IEEE 1149.1)
• De-chip voltage moderator (VREG) pro ordinatione
input supplent omnes gradus interiores.
